1. Field of the Invention
The present invention relates to a semiconductor package and a method for manufacturing the semiconductor package, and more particularly, to a wafer level semiconductor package and a method for manufacturing the semiconductor package at wafer level.
2. Description of the Related Art
The semiconductor package has four major functions, i.e. signal distribution, power distribution, heat dissipation, and protection. In general, the semiconductor chip is formed into an enclosure, such as a single-chip module (SCM) or a chip carrier, referred to as the packaging of the semiconductor. These packaged chips, along with other components such as capacitors, resistors, inductors, filters, switches, and optical and RF components, are assembled to a printed wiring board.
As the need has arisen for lighter and more complex electronic devices, the velocity and the complexity of IC chip become more and more higher. Accordingly, a need has arisen for higher package efficiency. Prior art attempts have been made to provide various packages and manufacturing methods for increasing the efficiency and the reliability of the package. For example, U.S. Pat. No. 6,040,235 entitled “Methods And Apparatus For Producing Integrated Circuit Devices,” issued to Badehi on May 21, 2000, and U.S. Pat. No. 6,117,707 entitled “Methods Of Producing Integrated Circuit Devices,” issued to Badehi on Sep. 12, 2000 disclose methods for manufacturing the semiconductor packages. However, the semiconductor package and the manufacturing method in the prior art still have many drawbacks, such as low reliability and electrical performance, large volume, and high manufacturing cost, and the need of semiconductor package was not fulfilled.
Accordingly, there exists a need for a semiconductor package manufactured at wafer level so as to further fulfill the demands of the semiconductor package.